Simone Machetti, PhD

About

Researcher with 7+ years of experience in low-power heterogeneous architectures, specializing in RISC-V platforms, accelerator integration (CGRA, IMC, NMC), and GPU design for AI applications. Experienced in both silicon tapeouts (65 nm, 16 nm) and FPGA prototyping. Author of 10+ publications in top conferences and journals (ICCAD, ISVLSI, IEEE Micro, TBioCAS), with 200+ citations. Co-organizer of international workshops, teaching assistant in ASIC/FPGA design, and active contributor to open-source frameworks (FEMU, X-HEEP, e-GPU).

• RTL Design
• ASIC Design
• FPGA Design
• SoC Design
• RISC-V
• Accelerator Integration
• GPU Architecture
• Silicon Tapeout
• FPGA Prototyping

Hardware

SystemVerilog, Verilog, VHDL

Commercial EDA

ModelSim, Design Compiler, Innovus, PrimeTime, PrimePower, Vivado

Open-source EDA

Verilator, Yosys, OpenROAD, OpenSTA

Software

C, C++, RISC-V assembly

Scripting

Python, Tcl, Bash, Git

Experience

Several years in low-power hardware

1. Feb 2026 – PresentZurich, Switzerland

   Research Scientist

   Huawei

   Driving research on advanced computing architectures for energy-efficient AI processing at the Von Neumann Research Center (VNRC).

2. Apr 2026 – May 2026Shanghai, China

   Visiting Researcher

   HiSilicon

   Conducted research on the optimization of matrix multiplication accelerators for next-generation AI processors.

3. Jan 2025 – Oct 2025Lausanne, Switzerland

   Research Member

   SwissChips

   Contributed to the SwissChips project, which advances open-source and energy-efficient hardware design in Switzerland.

4. Jul 2020 – Oct 2025Lausanne, Switzerland

   PhD Researcher

   EPFL, Embedded Systems Laboratory

   Conducted research across multiple topics in the design of ASIC and FPGA frameworks and platforms for TinyAI applications.

   Main contributions

   • FPGA EMUlation (FEMU): an open-source and configurable emulation framework for prototyping and evaluating TinyAI heterogeneous systems.
   • eXtendible Heterogeneous Energy-Efficient Platform (X-HEEP): an open-source, configurable, and extendible RISC-V platform that supports the exploration of TinyAI accelerators.
   • Embedded GPU (e-GPU): an open-source and configurable RISC-V platform for exploring the feasibility and trade-offs of using GPUs in TinyAI scenarios.

   Tapeouts

   • HEEPocrates (65 nm TSMC): integrates the X-HEEP host with a coarse-grained reconfigurable array (CGRA) and in-memory computing (IMC) accelerators.
   • HEEPatia (16 nm TSMC): integrates the X-HEEP host with a coarse-grained reconfigurable array (CGRA), near-memory computing (NMC) accelerators, and a co-processor for posit arithmetic.

   Workshops

   • DATE 2024 Conference: co-organized a workshop on RISC-V open-source hardware and software, and presented my research activities.

   Competitions

   • AMD Open Hardware Competition: designed an emulation platform for exploring TinyAI heterogeneous systems.

   Honors

   • Best Project Award: awarded by the SMARTHEP Edge Machine Learning School at CERN, Geneva.

5. Jul 2020 – Oct 2025Lausanne, Switzerland

   Teaching Assistant

   EPFL

   Assisted in teaching multiple courses on ASIC and FPGA implementation flows.

   • Lab in advanced VLSI design: the complete ASIC design flow, from RTL to GDS (Prof. Andreas Burg).
   • Digital systems design: the entry-level FPGA design flow, using Xilinx FPGAs (Prof. Andreas Burg).
   • Lab on hardware-software digital systems co-design: the design of complex hardware/software architectures on Xilinx FPGAs (Prof. David Atienza).

6. Jul 2020 – Oct 2025Lausanne, Switzerland

   Co-Founder & Senior Researcher

   X-HEEP Platform

   Co-founded and contributed to a university project focused on the development of open-source, configurable, and extendible RISC-V hardware. The project is built around the eXtendible Heterogeneous Energy-Efficient Platform (X-HEEP), a configurable and extendible RISC-V host designed to support the exploration of ultra-low-power edge accelerators.

7. Nov 2019 – Jun 2020Lausanne, Switzerland

   Research Intern

   EPFL, Embedded Systems Laboratory

   Implemented and optimized convolutional neural networks (CNNs) on ultra-low-power heterogeneous multi-core architectures, in a project carried out in collaboration with Nespresso.

8. Nov 2019 – Jun 2020Lausanne, Switzerland

   External Researcher

   Nestlé Nespresso SA

   Collaborated with Nespresso during my internship at the Embedded Systems Laboratory (ESL) of EPFL, working on the implementation and optimization of convolutional neural networks (CNNs) on ultra-low-power heterogeneous multi-core architectures.

9. Jan 2019 – Oct 2019Volpiano, Italy

   Firmware Engineer

   SPEA

   Developed low-level firmware implementing various functionalities of automatic test equipment (ATE). Trained in the use of the complete laboratory equipment, including oscilloscopes, multimeters, waveform generators, and soldering irons.

Education

A curriculum focused on RTL design

• 2020 – 2025

  PhD in Electrical and Electronics Engineering

  EPFL

  Completed at the Embedded Systems Laboratory (ESL) of EPFL, under the supervision of Professor David Atienza.

  Thesis title: Open-Source and Configurable RISC-V Platforms for Exploring TinyAI Heterogeneous Systems.

• 2016 – 2018

  MSc in Computer Engineering, major in Embedded Systems

  Politecnico di Torino

  Grade: 110/110 summa cum laude · Grade average: 29.5/30

  Thesis title: ASIP Design for Motion Estimation in Video Compression Algorithms.

  Designed an application-specific instruction-set processor (ASIP) core optimized for video compression applications, using Synopsys ASIP Designer to describe, compile, and simulate the processor.

  RTL projects

  • CPU RTL Design: a DLX microprocessor core with a five-stage pipeline.
  • Filter RTL Design: a finite impulse response (FIR) low-pass filter, designed at different abstraction levels.
  • Multiplier RTL Design: a modified Booth encoding (MBE) multiplier.
  • Sniffer RTL Design: a bus sniffer that monitors the instruction bus of an MCU and activates hardware Trojans.
  • Interface RTL Design: a smart and efficient communication protocol between an MCU and an FPGA.

• 2013 – 2016

  BSc in Computer Engineering

  Politecnico di Torino

  Project

  • Smart Bus Station: a smart bus station designed to support visually impaired people in using the public transport system.

Selected publications

Research on RISC-V platforms and AI hardware

1. X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators arXiv, 2024

   Link

2. Modular Design and Optimization of Biomedical Applications for Ultralow Power Heterogeneous Platforms IEEE TCAD, 2020

   Link

3. A Hardware/Software Co-Design Vision for Deep Learning at the Edge IEEE Micro, 2022

   Link

4. X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller ACM Computing Frontiers, 2023

   Link

5. Defeating Hardware Trojan in Microprocessor Cores through Software Obfuscation IEEE LATS, 2018

   Link

6. X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications ISVLSI, 2025

   Link

7. HEEPocrates: An Ultra-Low-Power RISC-V Microcontroller for Edge-Computing Healthcare Applications Europractice Activity Report, 2023

   Link

8. ACE: Automated Optimization Towards Iterative Classification in Edge Health Monitors IEEE TBioCAS, 2024

   Link

9. e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications arXiv, 2025

   Link

10. ASIP Design for Motion Estimation in Video Compression Algorithms MSc thesis, Politecnico di Torino, 2018

    Link

11. An Open-Source and Configurable RISC-V CPU/GPU Accelerated Processing Unit for Ultra-Low-Power Wearable Devices SMARTHEP Edge Machine Learning School, CERN, 2024

    Link

12. FEMU: An Open-Source RISC-V Emulation Platform for the Exploration of Accelerator-based Edge Applications DATE, 2024

    Link

13. FEMU: An Open-Source and Configurable Emulation Framework for Prototyping TinyAI Heterogeneous Systems ICCAD, 2025

    Link

14. Open-Source and Configurable RISC-V Platforms for Exploring TinyAI Heterogeneous Systems PhD thesis, EPFL, 2025

    Link

15. X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators EcoCloud Event, EPFL, 2023

    Link

Main open-source projects

• Co-founder

  X-HEEP

  An open-source, configurable, and extendible RISC-V microcontroller built to host ultra-low-power edge accelerators. Taped out in the HEEPocrates (65 nm) and HEEPatia (16 nm) chips, and maintained by EPFL, UPM, and Politecnico di Torino.

  GitHub Paper

• Lead author

  FEMU

  An FPGA emulation framework for prototyping and evaluating TinyAI heterogeneous systems. It ports X-HEEP to the Zynq-7020 of a Pynq-Z2 board, so applications can be explored on real hardware before silicon exists.

  GitHub Paper

• Lead author

  FEMU SDK

  The software development kit for FEMU. It runs on the Linux side of the board and allows users to run their own applications on the emulated X-HEEP, from a terminal or a Jupyter environment.

  GitHub Paper

• Lead author

  e-GPU

  An open-source, configurable RISC-V GPU for TinyAI devices, programmed through a lightweight Tiny-OpenCL framework. Paired with X-HEEP as an accelerated processing unit and implemented in 16 nm within a 28 mW power budget.

  GitHub Paper

• Author

  RTL Sandbox Template

  A GitHub template for RTL research projects. It ships a complete open-source ASIC flow on the ASAP7 predictive PDK: Verilator simulation, Yosys synthesis, OpenROAD place-and-route, and OpenSTA timing and power analysis.

  GitHub

• Author

  ASAP7 SMIC N+3 BEOL

  The ASAP7 predictive PDK with a swappable metal stack, rebuilt on the pitches measured on SMIC N+3. One design can be placed and routed on both stacks, to compare results against a process with no public design kit.

  GitHub

Highlights